Low leakage switches are of importance in sample and hold systems with long hold times, as for example for reference current or reference voltage circuits. Especially, at elevated temperatures, leakage currents become an error source. Many electronic devices, as for example integrated semiconductor circuits, sample an input or reference voltage on a capacitor. One side of the sampling capacitor is coupled to an input voltage through a sampling switch. The sampling switch is closed (conducting) and the sampling capacitor is charged (sampling phase or sampling time). After having sampled the voltage on the sampling capacitor, the sampling switch is opened (not conducting).
One purpose of sampling a certain voltage level is to extend the time period (hold phase or hold time) during which the sampling switch is not conducting. This aims to preserve the sampled voltage on the sampling capacitor as long as possible which means that the charge on the sampling capacitor must be preserved. However, many characteristics of real integrated circuits adversely affect charge preservation. A drawback is the leakage current through the sampling switches. In a conventional approach it may be possible to overcome this effect merely by increasing the capacitance value of the sampling capacitor. However, this means increasing the size of the capacitor which is similar to increasing chip area and thereby costs of the integrated circuits. Larger capacitors can further increase power consumption if the same speed should be maintained as for smaller capacitors. Other solutions aim to improve the sampling switches.
Sampling switches are implemented with transistors. In a CMOS technology a switch may be an NMOS, a PMOS transistor or a combination of both referred to as a transmission gate. MOS transistors have P-doped regions and N-doped regions which can form parasitic diodes. One of these diodes is referred to as backgate diode as it couples the source or the drain of the transistor to the backgate being located opposite to the control gate. In a simplified model of a real MOS transistor a backgate diode may be located between drain and source of the transistor and the backgate. In order to avoid leakage currents through these backgate diodes, the voltage level on the backgate (or backgate) is controlled such that the backgate diodes are reversely biased. However, even with reverse bias a minimum saturation current can flow through the backgate diode and the voltage level on the sampling capacitor can change significantly.
FIG. 1 shows a simplified circuit diagram of a low leakage switch 2 according to the prior art and as disclosed in German patent 10 2009 008 757 of Texas Instruments. The switch 2 includes MOS transistors P1, P2 and P3. Each of the MOS transistors P1, P2 and P3 is coupled to an input node so as to receive the input voltage IN. The (control) gates are controlled with sampling clock signal SMPL. The first transistor P1 of the cascade is coupled with its source/drain junction to the sampling capacitor CS. The second transistor P2 of the cascade is coupled with its source/drain junction to a first buffer capacitor CSB1 and to a backgate BG1 (bulk of P1) of the first transistor P1. The third transistor P3 of the cascade is coupled with its source/drain junction to the backgate BG2 of the second transistor P2 and with its own backgate BG3 to a tap node between transistors P4 and P5. P5 is configured to couple the backgate BG3 of the third transistor to supply voltage level VSUP during the hold phase. P4 is configured to couple the backgate BG3 of transistor P3 to the input voltage IN during the sampling phase. All transistors P1 to P3 of the cascade are simultaneously switched. Buffer capacitors CSB1 and CSP2 are provided and coupled to the backgates BG1 and BG2 of transistors P1 and P2. Only the backgate BG3 of the last transistor P3 of the cascade is either coupled to the input voltage during the sampling phase or to the supply voltage level during the hold phase. The input voltage is sampled on the sampling capacitor CS and also on the buffer capacitors CSB1 and CSB2.
During the sampling phase (SMPL=1, SMPL is logic high), transistors P1, P2, P3 and P4 are conducting and capacitors CS, CSB1 and CSB2 are charged to the input voltage level IN. Furthermore, the backgate BG3 of transistor P3 is coupled to the input voltage IN. The input voltage is also sampled and stored on the input capacitor CSI. This reduces channel leakage of P1, P2 and P3 reduces channel leakage from the capacitors CS, CSB1 and CSB2 to the input IN. During the hold phase (SMPL=0, SMPL is logic low), both backgate diodes D6 and D4 are reversely biased as the tap node between P4 and P5—to which backgate BG3 is coupled—is tied to positive supply voltage level VSUP. The voltage on CSB2 and therefore the backgate voltage start to change due to a leakage current through diode D4. Backgate diode D3 of transistor P2 is initially zero biased (also D5) and the voltage on backgate BG1 remains unchanged.
Although the previously described low leakage switch achieves good performance, it is desirable to further improve the leakage currents, in particular for current or voltage reference stages.